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39.8.6 READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller
- Wait until the current command execution has successfully
completed.
- Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
- Program the block length in the card. This value defines the value block_length.
- Program the block length in the HSMCI Configuration Register with block_length value.
- Set RDPROOF bit in HSMCI_MR to avoid overflow.
- Configure the fields of the HSMCI_MR as follows:
- Program FBYTE to one when the transfer is not multiple of 4, zero otherwise.
- Issue a READ_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK command.
- Program the DMA controller.
- Read the Channel Status Register to choose an available (disabled) channel.
- Clear any pending interrupts on the channel from the previous DMA transfer by
reading the DMAC_CISx register.
- Program the channel registers.
- The DMAC_CSAx register for Channel x must be set with the starting address of the
HSMCI_FIFO address.
- The DMAC_CDAx register for Channel x must be word aligned.
- Configure the fields of DMAC_CCx for Channel x as follows:
- DWIDTH is set to WORD when the length is a multiple of 4, otherwise it is
set to BYTE
- CSIZE must be set according to the value of HSMCI_DMA.CHKSIZE
- Configure the fields of the DMAC_CUBCx register of Channel x as follows:
- UBLEN is programmed with block_length/4 when the transfer length is
multiple of 4, block_length otherwise
- Enable Channel x, writing one to DMAC_GE.EN[x]. The DMAC is ready and waiting for
request.
- Wait for XFRDONE in the HSMCI_SR.