33.11.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle therefore only occurs between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
- If the write controlling signal has no hold time and the read
controlling signal has no setup time , as shown in the following figure:
Figure 33-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup - In NCS Write controlled mode (SMC_MODE.WRITE_MODE = 0), if there
is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0,
regardless of the Read mode, as shown in the following figure. The write operation must
end with a NCS rising edge. Without an Early Read Wait State, the write operation could
not complete properly.
Figure 33-19. Early Read Wait State: NCS-controlled write with no hold followed by a read with no NCS setup - In NWE controlled mode (SMC_MODE.WRITE_MODE = 1) and if there is
no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to
control address, data, and chip select lines. If the external write control signal is
not inactivated as expected due to load capacitances, an Early Read Wait State is
inserted and address, data and control signals are maintained one more cycle. See the
following figure.
Figure 33-20. Early Read Wait State: NWE-controlled write with no hold followed by a read with one set-up cycle