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PIC32CZ CA70/MC70 Family Data Sheet  PIC32CZ CA70/MC70
PIC32CZ CA70/MC70 Family Data Sheet PIC32CZ CA70/MC70
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  2. 33 Static Memory Controller (SMC)
  3. 33.4 Multiplexed Signals

PIC32CZ CA70/MC70

  • 32-bit Arm Cortex-M7 MCUs with FPU, Audio and Graphics Interfaces, High-Speed USB, Ethernet, and Advanced Analog
  • 1 Configuration Summary
  • 2 Guidelines for Getting Started
  • 3 Ordering Information
  • 4 Block Diagram
  • 5 Package and Pinout
  • 6 Signal Description
  • 7 Power Supplies
  • 8 Device Startup
  • 9 Product Mapping
  • 10 Input/Output Lines
  • 11 Peripherals
  • 12 Memories
  • 13 Processor and Architecture
  • 14 Debug and Test Features
  • 15 Event System
  • 16 System Controller
  • 17 In-Application Programming (IAP)
  • 18 Fast Flash Programming Interface (FFPI)
  • 19 Bus Matrix (MATRIX)
  • 20 Chip Identifier (CHIPID)
  • 21 Enhanced Embedded Flash Controller (EEFC)
  • 22 Clock Generator
  • 23 Power Management Controller (PMC)
  • 24 Supply Controller (SUPC)
  • 25 Watchdog Timer (WDT)
  • 26 Reinforced Safety Watchdog Timer (RSWDT)
  • 27 Reset Controller (RSTC)
  • 28 Real-Time Clock (RTC)
  • 29 Real-Time Timer (RTT)
  • 30 General Purpose Backup Registers (GPBR)
  • 31 Parallel Input/Output Controller (PIO)
  • 32 External Bus Interface (EBI)
  • 33 Static Memory Controller (SMC)
    • 33.1 Description
    • 33.2 Embedded Characteristics
    • 33.3 I/O Lines Description
    • 33.4 Multiplexed Signals
    • 33.5 Product Dependencies
    • 33.6 External Memory Mapping
    • 33.7 Connection to External Devices
    • 33.8 Application Example
    • 33.9 Standard Read and Write Protocols
    • 33.10 Scrambling/Unscrambling Function
    • 33.11 Automatic Wait States
    • 33.12 Data Float Wait States
    • 33.13 External Wait
    • 33.14 Slow Clock Mode
    • 33.15 Asynchronous Page Mode
    • 33.16 Register Summary
  • 34 DMA Controller (XDMAC)
  • 35 Image Sensor Interface (ISI)
  • 36 Ethernet MAC
  • 37 USB Transmitter Macrocell Interface (UTMI)
  • 38 USB High-Speed Interface (USBHS)
  • 39 High-Speed Multimedia Card Interface (HSMCI)
  • 40 Serial Peripheral Interface (SPI)
  • 41 Quad Serial Peripheral Interface (QSPI)
  • 42 Two-wire Interface (TWIHS)
  • 43 Synchronous Serial Controller (SSC)
  • 44 Inter-IC Sound Controller (I2SC)
  • 45 Universal Synchronous Asynchronous Receiver Transceiver (USART)
  • 46 Universal Asynchronous Receiver Transmitter (UART)
  • 47 Media Local Bus (MLB)
  • 48 Controller Area Network (CAN)
  • 49 Timer Counter (TC)
  • 50 Pulse Width Modulation (PWM) Controller
  • 51 Analog Front-End Controller (AFEC)
  • 52 Digital-to-Analog Converter Controller (DACC)
  • 53 Analog Comparator Controller (ACC)
  • 54 Integrity Check Monitor (ICM)
  • 55 True Random Number Generator (TRNG)
  • 56 Advanced Encryption Standard (AES)
  • 57 Electrical Specifications 85°C
  • 58 Electrical Specifications 105°C
  • 59 Packaging Information
  • 60 Schematic Checklist
  • 61 Conventions
  • 62 Acronyms and Abbreviations
  • 63 Appendix A
  • 64 Appendix B
  • 65 Revision History
  • Microchip Information

33.4 Multiplexed Signals

Table 33-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed SignalsRelated Function
NWR0NWEByte-write or Byte-select access.

See ”Byte Write Access” and ”Byte Select Access”

A0NBS08-bit or 16-bit data bus. See ”Data Bus Width”
NWR1NBS1Byte-write or Byte-select access. See ”Byte Write Access” and ”Byte Select Access”
A22NANDCLENAND Flash Command Latch Enable
A21NANDALENAND Flash Address Latch Enable

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