52.7.6 DACC Channel Status Register
| Name: | DACC_CHSR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DACRDY1 | DACRDY0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CH1 | CH0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bits 8, 9 – DACRDYx DAC Ready Flag
| Value | Description |
|---|---|
| 0 | The DACx is not yet ready to receive data. |
| 1 | The DACx is ready to receive data. |
Bits 0, 1 – CHx Channel x Status
| Value | Description |
|---|---|
| 0 | Corresponding channel is disabled. |
| 1 | Corresponding channel is enabled. |