23.4 Host Clock Controller

The Host Clock Controller provides the Host Clock (MAIN_CLK) with the selection and division of the clock generator's output signals. MAIN_CLK is the source clock of the peripheral clocks.

The clock to be selected between SLOW_CLK, MAIN_CLK, PLLA_CLK and UPLL_CLK_DIV is configured in PMC_MCKR.CSS. The prescaler supports the 1, 2, 3, 4, 8, 16, 32, 64 division factors and is configured using PMC_MCKR.PRES.

Each time PMC_MCKR is configured to define a new MAIN_CLK, the MCKRDY bit is cleared in PMC_SR. It reads ‘0’ until MAIN_CLK is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is completed.

Note: Users cannot modify MDIV and CSS at the same access. Each field must be modified separately with a wait for the MCKRDY flag between the first field modification and the second field modification.