51.7.20 AFEC Channel Offset Compensation Register

This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.

Name: AFEC_COCR
Offset: 0x6C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       AOFF[9:8] 
Access R/WR/W 
Reset 00 
Bit 76543210 
 AOFF[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 9:0 – AOFF[9:0] Analog Offset

Defines the analog offset to be used for channel CSEL (configured in the AFEC Channel Selection Register). This value is used as an input value for the DAC included in the AFE.

Note: The field AOFF must be configured to 512 (mid scale of the DAC) when there is no offset error to compensate. To compensate for an offset error of n LSB (positive or negative), the field AOFF must be configured to 512 + n.

The value of the AOFF bit can be updated only if the AFEC module is restarted, or if two conversions are run; the second one will have the correct AOFF bit setting.