28.9.2 SSPxCON1

MSSP Control Register 1
Note:
  1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
  2. When enabled, these pins must be properly configured as inputs or outputs.
  3. SSPxADD = 0 is not supported.
  4. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
Name: SSPxCON1
Address: 0xF95,0xE91

Bit 76543210 
 WCOLSSPOVSSPENCKPSSPM[3:0] 
Access R/W/HSR/W/HSR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – WCOL

Write Collision Detect bit
ValueNameDescription
1 SPI A write to the SSPxBUF register was attempted while the previous byte was still transmitting (must be cleared by software)
1 I2C Master transmit A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared by software)
1 I2C Slave transmit The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 SPI or I2C Master or Slave transmit No collision
x Master or Slave receive Don’t care

Bit 6 – SSPOV

Receive Overflow Indicator bit(1)
ValueNameDescription
1 SPI Slave A byte is received while the SSPxBUF register is still holding the previous byte. The user must read SSPxBUF, even if only transmitting data, to avoid setting overflow. (must be cleared in software)
1 I2C Receive A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software)
0 SPI Slave or I2C Receive No overflow
x SPI Master or I2C Master transmit Don’t care

Bit 5 – SSPEN

Master Synchronous Serial Port Enable bit.(2)
ValueNameDescription
1 SPI Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be made with the PPS controls. Each signal must be configured with the corresponding TRIS control to the direction appropriate for the mode selected.
1 I2C Enables the serial port. The SDAx and SCLx pin selections must be made with the PPS controls. Since both signals are bidirectional the PPS input pin and PPS output pin selections must be made that specify the same pin. Both pins must be configured as inputs with the corresponding TRIS controls.
0 All Disables serial port and configures these pins as I/O PORT pins

Bit 4 – CKP

SCK Release Control bit
ValueNameDescription
1 SPI Idle state for the clock is a high level
0 SPI Idle state for the clock is a low level
1 I2C Slave Releases clock
0 I2C Slave Holds clock low (clock stretch), used to ensure data setup time
x I2C Master Unused in this mode

Bits 3:0 – SSPM[3:0]

Master Synchronous Serial Port Mode Select bits(4)
ValueDescription
1111 I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled
1110 I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled
1101 Reserved - do not use
1100 Reserved - do not use
1011 I2C Firmware Controlled Master mode (slave Idle)
1010 SPI Master mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3)
1001 Reserved - do not use
1000 I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1))
0111

I2C Slave mode: 10-bit address

0110 I2C Slave mode: 7-bit address
0101 SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled
0100 SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled
0011 SPI Master mode: Clock = TMR2 output/2
0010 SPI Master mode: Clock = Fosc/64
0001 SPI Master mode: Clock = Fosc/16
0000 SPI Master mode: Clock = Fosc/4
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as inputs or outputs. SSPxADD = 0 is not supported. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.