28.9.1 SSPxSTAT

MSSP Status Register

Note:

This bit is cleared on Reset and when SSPEN is cleared.
In I²C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
Polarity of clock state is set by the CKP bit.
I²C receive status does not include ACK and Stop bits.

Name:	SSPxSTAT
Address:	0xF94,0xE90


Bit	7	6	5	4	3	2	1	0
	SMP	CKE	D/A	P	S	R/W	UA	BF
Access	R/W	R/W	RO	RO	RO	RO	RO	RO
Reset	0	0	0	0	0	0	0	0

Bit 7 – SMP Slew Rate Control bit

Value	Name	Description
`1`	SPI Master	Input data is sampled at the end of data output time
`0`	SPI Master	Input data is sampled at the middle of data output time
`0`	SPI Slave	Keep this bit cleared in SPI Slave mode
`1`	I²C	Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)
`0`	I²C	Slew rate control is enabled for High-Speed mode (400 kHz)

Bit 6 – CKE

SPI: Clock select bit⁽⁴⁾ I²C: SMBus Select bit

Value	Name	Description
`1`	SPI	Transmit occurs on the transition from active to Idle clock state
`0`	SPI	Transmit occurs on the transition from Idle to active clock state
`1`	I²C	Enables SMBus-specific inputs
`0`	I²C	Disables SMBus-specific inputs

Bit 5 – D/A

Data/Address bit

Value	Name	Description
`x`	SPI or I²C Master	Reserved
`1`	I²C Slave	Indicates that the last byte received or transmitted was data
`0`	I²C Slave	Indicates that the last byte received or transmitted was address

Bit 4 – P

Stop bit⁽¹⁾

Value	Name	Description
`x`	SPI	Reserved
`1`	I²C	Stop bit was detected last
`0`	I²C	Stop bit was not detected last

Bit 3 – S

Start bit⁽¹⁾

Value	Name	Description
`x`	SPI	Reserved
`1`	I²C	Start bit was detected last
`0`	I²C	Start bit was not detected last

Bit 2 – R/W

Read/Write Information bit^(2,3)

Value	Name	Description
`x`	SPI	Reserved
`1`	I²C Slave	Read
`0`	I²C Slave	Write
`1`	I²C Master	Transmit is in progress
`0`	I²C Master	Transmit is not in progress

Bit 1 – UA Update Address bit (10-Bit Slave mode only)

Value	Name	Description
`x`	All other modes	Reserved
`1`	I²C 10-bit Slave	Indicates that the user needs to update the address in the SSPxADD register
`0`	I²C 10-bit Slave	Address does not need to be updated

Bit 0 – BF

Buffer Full Status bit⁽⁵⁾

Value	Name	Description
`1`	I²C Transmit	Character written to SSPxBUF has not been sent
`0`	I²C Transmit	SSPxBUF is ready for next character
`1`	SPI and I²C Receive	Received character in SSPxBUF has not been read
`0`	SPI and I²C Receive	Received character in SSPxBUF has been read

This bit is cleared on Reset and when SSPEN is cleared. In I2C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. Polarity of clock state is set by the CKP bit. I2C receive status does not include ACK and Stop bits.