8.4.1 PMD0

PMD Control Register 0
Note:
  1. Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected.
  2. Subject to SCANE bit in Configuration Word 4.
  3. When enabling NVM, a delay of up to 1 µs is required before accessing data.
Name: PMD0
Address: 0xEDC

Bit 76543210 
 SYSCMDFVRMDHLVDMDCRCMDSCANMDNVMMDCLKRMDIOCMD 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – SYSCMD Disable Peripheral System Clock Network bit

Disables the System clock network(1)

ValueDescription
1

System clock network disabled (FOSC)

0

System clock network enabled

Bit 6 – FVRMD Disable Fixed Voltage Reference bit

ValueDescription
1

FVR module disabled

0

FVR module enabled

Bit 5 – HLVDMD Disable High-Low-Voltage Detect bit

ValueDescription
1

HLVD module disabled

0

HLVD module enabled

Bit 4 – CRCMD Disable CRC Engine bit

ValueDescription
1

CRC module disabled

0

CRC module enabled

Bit 3 – SCANMD Disable NVM Memory Scanner bit

Disables the Scanner module(2)

ValueDescription
1

NVM Memory Scan module disabled

0

NVM Memory Scan module enabled

Bit 2 – NVMMD NVM Module Disable bit

Disables the NVM module(3)

ValueDescription
1

All Memory reading and writing is disabled; NVMCON registers cannot be written

0

NVM module enabled

Bit 1 – CLKRMD Disable Clock Reference bit

ValueDescription
1

CLKR module disabled

0

CLKR module enabled

Bit 0 – IOCMD Disable Interrupt-on-Change bit, All Ports

ValueDescription
1

IOC module(s) disabled

0

IOC module(s) enabled

Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected.Subject to SCANE bit in Configuration Word 4.When enabling NVM, a delay of up to 1 µs is required before accessing data.