33.5.1 Digital Filter/Average

The digital filter/average module consists of an accumulator with data feedback options, and control logic to determine when threshold tests need to be applied. The accumulator is a 16-bit wide register that can be accessed through the ADACC33.7.17 ADACC registers.

Upon each trigger event (the ADGO bit set or external event trigger), the ADC conversion result is added to the accumulator. If the accumulated value exceeds 2(accumulator_width)-1 = 216 = 65535, the ADAOV overflow bit is set.

The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register. Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated (ADCNT = ADRPT), an accumulator clear command can be issued by the software by setting the ADACLR bit. Setting the ADACLR bit will also clear the ADAOV (Accumulator overflow) bit, as well as the ADCNT register. The ADACLR bit is cleared by the hardware when accumulator clearing action is complete.
Important: When ADC is operating from FRC, five FRC clock cycles are required to execute the ADACC clearing operation.

The ADCRS bits control the data shift on the accumulator result, which effectively divides the value in accumulator (ADACC33.7.17 ADACC) registers. For the Accumulate mode of the digital filter, the shift provides a simple scaling operation. For the Average/Burst Average mode, the shift bits are used to determine number of samples for averaging. For the Low-pass Filter mode, the shift is an integral part of the filter, and determines the cutoff frequency of the filter. Table 33-5 shows the -3 dB cutoff frequency in ωT (radians) and the highest signal attenuation obtained by this filter at nyquist frequency (ωT = π).

Table 33-5. Low-pass Filter -3 dB Cutoff Frequency
ADCRS ωT (radians) @ -3 dB Frequency dB @ Fnyquist=1/(2T)
1 0.72 -9.5
2 0.284 -16.9
3 0.134 -23.5
4 0.065 -29.8
5 0.032 -36.0
6 0.016 -42.0