33.7.5 ADSTAT
Note:
- If ADCS =
1, and FOSC<FRC, the indicated status may not be valid.
| Name: | ADSTAT |
| Address: | 0xF60 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADAOV | ADUTHR | ADLTHR | ADMATH | ADSTAT[2:0] | |||||
| Access | R/C/HS/HC | RO | RO | R/C/HS/HC | RO | RO | RO | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – ADAOV ADC Accumulator Overflow bit
| Value | Description |
|---|---|
| 1 | ADC accumulator or ADERR calculation have overflowed |
| 0 | ADC accumulator and ADERR calculation have not overflowed |
Bit 6 – ADUTHR ADC Module Greater-than Upper Threshold Flag bit
| Value | Description |
|---|---|
| 1 | ADERR >ADUTH |
| 0 | ADERR≤ADUTH |
Bit 5 – ADLTHR ADC Module Less-than Lower Threshold Flag bit
| Value | Description |
|---|---|
| 1 | ADERR<ADLTH |
| 0 | ADERR≥ADLTH |
Bit 4 – ADMATH ADC Module Computation Status bit
| Value | Description |
|---|---|
| 1 | Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already updated |
| 0 | Associated registers/bits have not changed since this bit was last cleared |
Bits 2:0 – ADSTAT[2:0]
| Value | Description |
|---|---|
| 111 | ADC module is in 2nd conversion stage |
| 110 | ADC module is in 2nd acquisition stage |
| 101 | ADC module is in 2nd precharge stage |
| 100 | Not used |
| 011 | ADC module is in 1st conversion stage |
| 010 | ADC module is in 1st acquisition stage |
| 001 | ADC module is in 1st precharge stage |
| 000 | ADC module is not converting |