25.15.1 CWGxCON0
Note:
- This bit can only be set after
EN =
1; it cannot be set in the same cycle when EN is set.
| Name: | CWGxCON0 |
| Address: | 0x0F3F |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | LD | MODE[2:0] | |||||||
| Access | R/W | R/W/HC | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – EN CWG1 Enable bit
| Value | Description |
|---|---|
1 |
Module is enabled |
0 |
Module is disabled |
Bit 6 – LD CWG1 Load Buffers bit(1)
| Value | Description |
|---|---|
1 |
Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set |
0 |
Buffers remain unchanged |
Bits 2:0 – MODE[2:0] CWG1 Mode bits
| Value | Description |
|---|---|
111 |
Reserved |
110 |
Reserved |
101 |
CWG outputs operate in Push-Pull mode |
100 |
CWG outputs operate in Half-Bridge mode |
011 |
CWG outputs operate in Reverse Full-Bridge mode |
010 |
CWG outputs operate in Forward Full-Bridge mode |
001 |
CWG outputs operate in Synchronous Steering mode |
000 |
CWG outputs operate in Asynchronous Steering mode |