25.15.1 CWGxCON0

CWG Control Register 0
Note:
  1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.
Name: CWGxCON0
Address: 0x0F3F

Bit 76543210 
 ENLD   MODE[2:0] 
Access R/WR/W/HCR/WR/WR/W 
Reset 00000 

Bit 7 – EN CWG1 Enable bit

ValueDescription
1 Module is enabled
0 Module is disabled

Bit 6 – LD  CWG1 Load Buffers bit(1)

ValueDescription
1 Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set
0 Buffers remain unchanged

Bits 2:0 – MODE[2:0] CWG1 Mode bits

ValueDescription
111 Reserved
110 Reserved
101 CWG outputs operate in Push-Pull mode
100 CWG outputs operate in Half-Bridge mode
011 CWG outputs operate in Reverse Full-Bridge mode
010 CWG outputs operate in Forward Full-Bridge mode
001 CWG outputs operate in Synchronous Steering mode
000 CWG outputs operate in Asynchronous Steering mode
This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.