25.15.5 CWGxSTR

CWG Steering Control Register (1)

Note:
  1. The bits in this register apply only when MODE = '00x' (CWGxCON025.15.1 CWGxCON0, Steering modes).
  2. This bit is double-buffered when MODE = '001'.
Name: CWGxSTR
Address: 0x0F43

Bit 76543210 
 OVRDOVRCOVRBOVRASTRDSTRCSTRBSTRA 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' bit

ValueNameDescription
x STRy = 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
1 STRy = 0 and POLy = x CWGx'y' output is high
0 STRy = 0 and POLy = x CWGx'y' output is low

Bits 0, 1, 2, 3 – STRy  STR'y' Steering Enable bit(2)

ValueDescription
1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
0 CWGx'y' output is assigned to value of OVRy bit
The bits in this register apply only when MODE = '00x' (CWGxCON0CWGxCON0, Steering modes).This bit is double-buffered when MODE = '001'.