21.2 Timer2 Output

The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time the T2TMR value matches the T2PR value. This signal can be selected as an input to several other input modules:

• The ADC module, as an auto-conversion trigger
• CWG, as an auto-shutdown source
• The CRC memory scanner, as a trigger for triggered mode
• Gate source for odd numbered timers (Timer1, Timer3, etc.)
• Alternate SPI clock
• Reset signals for other instances of even numbered timers (Timer2, Timer4, etc.)

In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See “PWM Overview” and “Pulse-width Modulation” sections for more details on setting up Timer2 for use with the CCP and PWM modules.