21.8 Register Summary - Timer2
Address | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x0FAD | Reserved | |||||||||
0x0FAE | T6TMR | 7:0 | TxTMR[7:0] | |||||||
0x0FAF | T6PR | 7:0 | TxPR[7:0] | |||||||
0x0FB0 | T6CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
0x0FB1 | T6HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
0x0FB2 | T6CLKCON | 7:0 | CS[4:0] | |||||||
0x0FB3 | T6RST | 7:0 | RSEL[4:0] | |||||||
0x0FB4 | T4TMR | 7:0 | TxTMR[7:0] | |||||||
0x0FB5 | T4PR | 7:0 | TxPR[7:0] | |||||||
0x0FB6 | T4CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
0x0FB7 | T4HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
0x0FB8 | T4CLKCON | 7:0 | CS[4:0] | |||||||
0x0FB9 | T4RST | 7:0 | RSEL[4:0] | |||||||
0x0FBA | T2TMR | 7:0 | TxTMR[7:0] | |||||||
0x0FBB | T2PR | 7:0 | TxPR[7:0] | |||||||
0x0FBC | T2CON | 7:0 | ON | CKPS[2:0] | OUTPS[3:0] | |||||
0x0FBD | T2HLT | 7:0 | PSYNC | CPOL | CSYNC | MODE[4:0] | ||||
0x0FBE | T2CLKCON | 7:0 | CS[4:0] | |||||||
0x0FBF | T2RST | 7:0 | RSEL[4:0] |