39.3.3 Power-Down Current (IPD)(1,2)

Table 39-3. 
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units Conditions
VDD VREGPM Note
D200 IPD IPD Base b'11' Reserved

D200A

IPD IPD Base 0.6 4.0 12 μA 3.0V b'10'
D200B 50 90 μA 3.0V b'01'
D200C 170 280 μA 3.0V b'00'
D201 IPD_WDT Low-Frequency Internal Oscillator/WDT 0.9 5.0 13 μA 3.0V b'10'
D202* IPD_SOSC Secondary Oscillator (SOSC) 1.6 4.3 10 μA 3.0V b'10' SOSCPWR = 0
D203 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) 0.9 5.0 13 μA 3.0V b'10'
D204 IPD_FVR FVR 70 105 110 μA 3.0V b'10' or b'01' FVRCON = 0x81 or 0x84
D205 IPD_BOR Brown-out Reset (BOR) 30 60 63 μA 3.0V b'10'
D206 IPD_HLVD High/Low- Voltage Detect (HLVD) 22 μA 3.0V b'10'
D207 IPD_ADCA ADC - Active 330 μA 3.0V b'10' or b'01' ADC is converting (4)
D208 IPD_CMP Comparator 60 85 90 μA 3.0V b'10'

* - These parameters are characterized but not tested.

† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption.
  2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS.
  3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
  4. ADC clock source is FRC.