39.3.2 Supply Current (IDD)(1,2,4)

Table 39-2. 
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions
VDD Note
D100 IDDXT4 XT = 4 MHz — 490 770 μA 3.0V
D100A IDDXT4 XT = 4 MHz — 410 — μA 3.0V All PMD bits are '1'
D101 IDDHFO16 HFINTOSC = 16 MHz — 1.3 1.7 mA 3.0V
D101A IDDHFO16 HFINTOSC = 16 MHz — 1.1 — mA 3.0V All PMD bits are '1'
D102 IDDHFOPLL HFINTOSC = 64 MHz — 4.4 5.8 mA 3.0V
D102A IDDHFOPLL HFINTOSC = 64 MHz — 3.4 — mA 3.0V All PMD bits are '1'
D103 IDDHSPLL64 HS+PLL = 64 MHz — 4.3 5.7 mA 3.0V
D103A IDDHSPLL64 HS+PLL = 64 MHz — 3.3 — mA 3.0V All PMD bits are '1'
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 0.6 — mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 0.7 — mA 3.0V

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from 
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
  2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
  3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register).
  4. PMD bits are all in the default state, no modules are disabled.