44 Revision History

Revision A (December 2025)

This is the initial version of the document.

Revision B (March 2026)

This revision incorporates the following updates:

  • Sections:
    • Updated High-Speed Analog-to-Digital Converters, Peripheral Features, Analog Features, Qualification, Integrated Touch Controller (ITC), 3.3.12.2.1. DSP Multiply Instructions, 3.4.3.7. TAG Memory Parity, 3.4.3.7.1. TAG Operation, 3.4.3.8.1. Cache Mode, 3.4.4.4. Module Operation When Cache Enabled, 3.4.4.4.1. ISB Buffers, 4.1.1.1. Unique Device Identifier (UDID), 4.5.1. Execute from RAM, 8.6. Cryptographic Accelerator Module (CAM), 8.6.1.4. Asymmetric Crypto Engine, 10.6.5. INTTREG, 10.8. Interrupt Sequence, 11.4.7. Virtual Output Pins, 11.4.9. I/O Multiplexing with Multiple Peripherals, 11.4.10. Change Notice (CN), 11.4.10.1. CN Configuration and Operation, 11.4.11. I/O Integrity Module (IOIM), 12.4.3.2. Primary Oscillator Pin Functionality, 12.4.4. Internal Fast RC (FRC) Oscillator, 12.4.5. BFRC Oscillator, 12.4.6. Phase-Locked Loop (PLL), 12.4.6.3.1. Setup for Using PLL with the Primary Oscillator (POSC), 15. High-Resolution PWM with Fine-Edge Placement, 15.5.2.2.4. LLC Resonant Converter Mode, 15.5.2.3.1. Complementary Output Mode, 16. 40 MSPS Analog-to-Digital Converter (ADC), 16.6.3. Windowed Multiple Conversions, 16.5.4. Integration of the Multiple Samples, 18.4.1. Excitation Signal Generation, 18.4.2.1. ADC Input Selection and Coherent Demodulation, 18.4.2.1.1. ADC Trigger Signals, 18.4.2.2. Excitation Signal Feedback Delay, 18.4.2.3. CIC Filter, 18.4.2.3.2. Heterodyne (Synchronous Demodulation), Operating Modes, Register Source Mode, External Signal Source Mode, 18.4.2.3.4. Auto Shift of Filter Output, 18.4.3. CORDIC Block, 18.4.3. CORDIC Block, 18.5. Interrupts, 20.2. Architectural Overview, 22. Serial Peripheral Interface (SPI), 24.4.5.1.2. Handling GETMXDS CCC, 24.4.5.1.4. Handling ENTDAA, GETPID and GETDCR and 45. Product Identification System.
    • Added 16-Bit Resolution Mode, 16-bit Conversion Example, 24. Improved Inter-Integrated Circuit (I3C), 10.6.5 Vector Fail Address, and 15.5.2.6.3 PCI Output Control Priority.
    • Removed 3.4.3.6.4. Implications of Variable NVM Wait States, 3.4.3.9.2. Stream Buffers, 3.4.4.13.2. Cache Coherency After a BOOTSWP Event and 17. Integrated Touch Controller (ITC).
    • Split 40 MSPS Analog-to-Digital Converter (ADC) and Integrated Touch Controller (ITC) into two separate sections.
  • Registers:
    • Updated 3.2.5 Core Mode Control Register, 3.2.6. Modulo Addressing Control Register, 3.2.8 X AGU Modulo Addressing End Register, 3.2.10 Y AGU Modulo Addressing End Register,3.2.15 Debug Hold PC Register , 3.4.2.5. Cache RAM Command Register (Address/Control), 6.2.22. NVM CRC Seed Register, 7.1.11. FPED Configuration Register, 8.2.10. Peripheral Access Control Register 3, 8.6.2.1. Crypto Accelerator Enable Register, 9.1.1. Reset Control Register, 9.4.6.1. Voltage Monitor Control Register, 9.4.6.3 Voltage Monitor Fault Injection Configuration Register, 10.4.6. Interrupt Control and Status Register, 10.4.13. Interrupt Request Flags Register 4, 10.4.24. Interrupt Enable Register 4, 10.4.48. Interrupt Priority Register 18, 10.4.49. Interrupt Priority Register 19, 12.3.2. Oscillator Configuration Register, 12.3.5. Clock Generator Control Register, 12.3.6. Clock Generator Divider Register, 12.3.7. PLL Control Register, 12.3.8. PLL Divider Register, 15.4.1. PWM Clock Control Register, 15.4.3. Frequency Scaling Minimum Period Register, 15.4.4. Master Phase Register, 15.4.8. Combinational Trigger Register, 15.4.9. Combinatorial PWM Logic Control Register, 15.4.10. PWM Event Output Control Register y, 15.4.11. PWM Generator x Control Register, 15.4.13. PWM Generator x I/O Control 1 Register, 15.4.14. PWM Generator x I/O Control 2 Register, 15.4.15. PWM Generator x Event 1 Register, 15.4.16. PWM Generator x Event 2 Register, 15.4.17. PWM Generator x F1 PCI 1 Register, 15.4.18. PWM Generator x F1 PCI 2 Register, 15.4.19. PWM Generator x F2 PCI 1 Register, 15.4.20. PWM Generator x F2 PCI 2 Register, 15.4.23. PWM Generator x Period Register, 15.4.27. PWM Generator x Leading-Edge Blanking Register, 15.4.28. PWM Generator x Phase Register, 15.4.29. PWM Generator x Duty Cycle Register, 15.4.30. PWM Generator x Dead-Time Register, 15.4.32. PWM Generator x Trigger A Register, 15.4.33. PWM Generator x Trigger B Register, 15.4.35. PWM Generator x Trigger D Register, 15.4.36. PWM Generator x Trigger E Register, 15.4.37. PWM Generator x Trigger F Register, 18.3.1. RDC Control Register, 18.3.2. RDC ADC Selection Register, 18.3.3. RDC Status Register, 18.3.4. RDC Excitation Signal Control Register, 18.3.5. RDC Excitation Signal Delay Register, 18.3.8. RDC CORDIC Block Angle Input Register, 18.3.13. CIC Status Register, 18.3.16. CIC Control 2 Register, 18.3.11. CIC Control 1 Register, 18.3.12. CIC Length Register, 18.3.13. CIC Status Register, 18.3.15. CIC Filter Input Timeout Counter Register, 18.3.18. CIC Channel x Input Register, 18.3.19. CIC Channel x Output Register, 18.3.20. CIC Channel x Decimated Accumulator Value Register, 19.3.5. DACx Data Register, 20.3.1. QEI 1 Control Register, 20.3.2. QEI 1 I/O Control Register, 20.3.3. QEI 1 Status Register, 22.3.1. SPIx Control Register 1, 28.3.2. CCPx Control Register 2, 37.2.2. Peripheral Module Disable 1 Register and 37.2.5. Peripheral Module Disable 4 Register.
    • Added 10.4.27 Interrupt Enable Register 7, 13.3.15 DMA Channel x Pattern Register, PWM Generator x CL PCI 1 Register, PWM Generator x CL PCI 2 Register, PWM Generator x FF PCI 1 Register, PWM Generator x FF PCI 2 Register, 15.4.25. PWM Generator x SP PCI 1 Register, 15.4.26. PWM Generator x S PCI 2 Register, 16.3.57 ADC 2 Channel x Secondary Accumulator Register, Peripheral Pin Select Output Register 32, Peripheral Pin Select Output Register 33,Peripheral Pin Select Output Register 34 and Peripheral Pin Select Output Register 35.
    • Removed 12.3.10. Reset Control Register because it is already in the Resets section.
  • Tables:
    • Updated Table 1. dsPIC33AK256MPS306 Family Device Features, Table 2. 36-Pin VQFN Complete Pin Function Descriptions, Table 3. 48-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 4. 64-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 5. Pinout I/O Descriptions, Table 9-2. Code Execution Start Time for Various Device Resets, Table 11-13. Output Selection for Remappable Pins (RPn), Table 12-3. Clock Generator Clock Resources, Table 12-4. PLL Clock Sources, Table 12-5. Clock Monitor Clock Resources, Table 12-6. Primary Oscillator Modes, Table 12-7. Clock Pin Function Selection, Table 12-8. PLL Mode Defaults, Table 13-7. RELOADS/RELOADD/RELOADC Bits and Data Transfer Modes, Table 14-2. CLKSEL Clock Selection bit,Table 15-2. MCLKSEL PWM Master Clock Selection, Table 16-2. ADC Input Availability, Table 16-4. Output Format, Table 18-2. CIC Block Summary, Table 21-2. UART Clock (FUART) Source Selection bits, Table 22-2. SPI Host Clock Source Selection bit, Table 26-2. CLKSEL Selection bit, Table 27-2. TCS Timer Clock Source Select bit, Table 28-2. CLKSEL Time Base Clock Select bits, Table 29-4. DS3 Data Selection MUX 3 Signal Selection bits, Table 42-2. Operating MHz vs. Voltage, Table 42-4. Thermal Packaging Characteristics, Table 42-10. DC Characteristics: PWM Delta Current, Table 42-12. DC Characteristics: PLL Delta Current, Table 42-13. DC Characteristics: ADC Δ Current, Table 42-14. DC Characteristics: Comparator + DAC Delta Current, Table 42-15. Op Amp Delta Current, Table 42-16. I/O Pin Input Specifications, Table 42-17. I/O Pin Input Leakage Specifications, Table 42-20. Capacitive Loading on Output Pins, Table 42-21. External Clock Timing Requirements, Table 42-22. PLLn Timing Specifications, Table 42-23. Peripheral Input Clock Timing Specifications, Table 42-24. Internal FRC Accuracy, Table 42-25. I/O Timing Requirements, Table 42-38. I3C Push-Pull Timing Parameters for SDR and HDR-DDR, Table 42-39. UARTx Module I/O Timing Requirements, Table 42-40. ADC Module Specifications, Table 42-42. High-Speed Analog Comparator Module Specifications and Table 42-46. Operational Amplifier Specifications.
    • Added Table 42-47. UREF Module Specification and Table 42-48. RDC Module Specification.
  • Figures:
    • Updated Figure 1-1. dsPIC33AK256MPS306 Family Block Diagram, Figure 6-3. Boot Sequence Number, Figure 9-3. Window Comp, Figure 10-4. Interrupt Latency, Figure 12-1. Oscillator Module Block Diagram, Figure 12-4. Clock Generator, Figure 12-9. PLL Block Diagram, Figure 15-15. Override and SWAP Signal Flow, Complementary Mode, Figure 12-2. Clock Generator, Figure 18-9. CIC Channel Block Diagram and Figure 24-1. I3C Hardware Block Diagram.
  • Examples:
    • Updated Example 11-1. Configuring UART1 Input and Output Functions, Example 11-2. Virtual PPS Connection, Example 11-3. IOIM Code, Example 11-4, Example 12-2. Code Example for Using PLL with the Primary Oscillator (POSC), Example 13-5. Code for Fixed to Block Continuous Transfer (Peripheral to Memory), Example 13-6. Null Write Mode, Example 18-1. RDC Configuration Code, Example 25-5. Short PWM Code (SPC) Support and Example 25-6. SENT Reception (SPC Pulse Transmission).
    • Removed Example 6-4. Partition Swap due to redundancy.
    • Equations:
  • Updated 12-8. FVCO Calculation and Equation 12-9. FPLLO Calculation.

Minor grammatical corrections and formatting changes have been made throughout the document.