In dsPIC33AK256MPS306 family devices, the
Configuration Words are implemented as volatile memory. This means that configuration data
will be loaded into volatile memory (from the Flash Configuration Words) each time the
device is powered up. Their specific locations are shown in Table 7-2. The configuration data are automatically
loaded from the Flash Configuration Words to the proper Configuration Shadow registers
during device Resets.
In the dsPIC33AK256MPS306 family, the configuration and
calibration data is duplicated in Flash for improved robustness. If a double ECC error is
detected during the start-up sequence, the device will restart the loading of the
calibration and configuration from the alternate set in Flash.
To maintain the integrity of the stored configuration values, logic performs ongoing bit
value checks. All device configuration bits are implemented as a complementary set of
register bits.
Table 7-1. Configuration Regions| Region | Address Range |
|---|
| CFGA1 | 0x7F3000 - 0x7F3800 |
| CFGB | 0x7F4000 - 0x7F4800 |
| CFGA2 | 0x7FB000 - 0x7FB800 |
Table 7-3. Device ID and Revision Addresses| Register | Address |
|---|
| DEVID | 0x7C2000 |
| DEVREV | 0x7C2004 |
Table 7-4. Family Device Identifier| Device | Device ID Value |
|---|
| dsPIC33AK128MPS303 | 0xB514 |
| dsPIC33AK128MPS305 | 0xB515 |
| dsPIC33AK128MPS306 | 0xB516 |
| dsPIC33AK256MPS303 | 0xB51C |
| dsPIC33AK256MPS305 | 0xB51D |
| dsPIC33AK256MPS306 | 0xB51E |
| dsPIC33AK128MPS103 | 0xB504 |
| dsPIC33AK128MPS105 | 0xB505 |
| dsPIC33AK128MPS106 | 0xB506 |
| dsPIC33AK256MPS103 | 0xB50C |
| dsPIC33AK256MPS105 | 0xB50D |
| dsPIC33AK256MPS106 | 0xB50E |