5.4.2.2 Performing Fault Injection

The following sequence should be followed to inject Faults.

  1. Load the data RAM target address into ECCFADDR register.

  2. Select the first Fault bit determined by ECCFPTRbits.FLT1PTR[5:0]. The data RAM target bit is inverted to create the Fault.

  3. If a double Fault is desired, select the second Fault bit determined by ECCFPTRbits.FLT2PTR[5:0], otherwise set ECCFPTR.FLT2PTR[5:0] = 6'h3F.

  4. This step applies only to partial read/write operations using PWB registers for a single memory location.
    • Perform read/write operations on more than four memory locations other than the target address before proceeding.
  5. Perform a read of the data RAM target address.
Note:
  1. RAM ECC registers operate in a 1:4 clock domain (see Figure 4.1) and are clocked by the Slow Speed Peripheral Clock. Software must allow sufficient delay after writing to these registers for the written values to propagate correctly.
  2. For PWB injection to work, its internal FIFO must be flushed. This ensures that data is read directly from memory rather than from the FIFO buffer.