29.1 Device-Specific Information

Table 29-1. CLC Summary Table
CLC Module Instances	Inputs per Instance	CLC Outputs	Peripheral Bus Speed
4	8	4	Slow (1:4 CPU Clock)

Table 29-3. DS2 Data Selection MUX 2 Signal Selection bits
Value (binary)	Description
`111`	Virtual Pin 8 Output
`110`	Virtual Pin 7 Output
`101`	Virtual Pin 6 Output
`100`	CLCINE
`011`	CLCIND
`010`	CLCINC
`001`	CLC2 Output
`000`	Slow Peripheral Clock (system clock/4)

Table 29-4. DS3 Data Selection MUX 3 Signal Selection bits
Value (binary)	Description
`111`	Virtual Pin 12 Output
`110`	Virtual Pin 11 Output
`101`	Virtual Pin 10 Output
`100`	Virtual Pin 9 Output
`011`	CLCING
`010`	CLCINF
`001`	CLC3 Output
`000`	BFRC/244⁽¹⁾
Note: Set the OSCCTRL.LPRCEN bit to '`1`' to enable the LPRC clock and observe it on the CLCxOUT pin.