19.1 Device-Specific Information

Table 19-1. DAC Summary
DAC Module Instances	Inputs per Instance	DAC Outputs	Clock Source	Peripheral Bus Speed
5	5 External, 1 Internal	1	CLKGEN7	Standard (1:2 CPU Clock)

Table 19-2. High-Speed Analog Comparator Module Availability
Comparator Input	36-Pin	48-Pin	64-Pin	PPS
ALLCMPNC		x	x	No
ALLCMPND		x	x	No
ALLCMPNE		—	x	No
ALLCMPNF		—	x	No
ALLCMPP	x	x	x	No
CMPP1A	x	x	x	No
CMPP1B	x	x	x	No
CMPP1C	x	x	x	No
CMPP1D		—	—	No
CMPP2A	x	x	x	No
CMPP2B	x	x	x	No
CMPP2C	x	x	x	No
CMPP2D		x	x	No
CMPP3A		x	x	No
CMPP3B		x	x	No
CMPP3C		x	x	No
CMPP3D		—	—	No
CMPP4A	x	x	x	No
CMPP4B	x	x	x	No
CMPP4C		x	x	No
CMPP4D	x	x	x	No
CMPP5A		x	x	No
CMPP5B		x	x	No
CMPP5C		—	x	No
CMPP5D		—	—	No

Table 19-3. Slope Start Signal Selection (SLPSTRT)
Slope Start Signal Selection	Source
7	RPV15
6	RPV14
5	RPV13
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 19-4. Slope Stop A Signal Select bits (SLPSTOPA)
Slope Stop A Signal Selection	Source
7	RPV15
6	RPV14
5	RPV13
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 19-5. Slope Stop B Signal Select bits (SLPSTOPB)
Slope Stop B Signal Selection	Source
7	RPV15
6	RPV14
5	RPV13
4	PWM4
3	PWM3
2	PWM2
1	PWM1
0	N/A

Table 19-6. Hysteretic Comparator Function Input Select Bits (HCFSEL)
Hysterectic Comparator Function Input Selection	Description
7	RPV15
6	RPV14
5	RPV13
4	PWM4H
3	PWM3H
2	PWM2H
1	PWM1H
0	N/A

The calibration register FPDMDAC is located in Flash at 0x7F20E0 with the POSINLADJ, NEGINLADJ and DNLADJ bit fields. The location should be copied and written to the corresponding bit fields in the DACCTRL1 SFR at start up.

Table 19-7. FPDMDAC Calibration Register
Name	Address Offset	Bit Field	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3
FPDMDAC	0x000	31:24	—	—	—	—	cfg_dac_filter[3:0]
		23:16	—	—	POSINLADJ[5:0]
		15:8	—	NEGINLADJ[6:0]
		7:0	—	—	—	DNLADJ[4:0]