3.4.2.5 Cache RAM Command Register (Address/Control)

Note:

When CACHE is enabled (CHECON.ON = 1 and CHECON.CP = 0), writes to the following register bits are ignored: RD, WP, WD, CMPP and CMPD.
If WD = 1 OR WP = 1, a write to the RD bit is ignored.
The CMPP and CMPD control bits require a minimum of three CPU clocks to complete the comparison and get set before reading the result.
The CMPD bit has priority over the RD bit. If the RD bit is set simultaneously with the CMPD bit, the read operation will be ignored because the data comparison operation has priority.

Name:	CHECMD
Offset:	0x1E7C


Bit	31	30	29	28	27	26	25	24
	RIP3	RIP2	RIP1	RIP0	WIP3	WIP2	WIP1	WIP0
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		CMPP	EWP	EWD	CMPD	RD
Access		R/W/HS/HC	W	W	R/W/HS/HC	W
Reset		0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			RVAL	WVAL	CMPV	WV
Access			R	W	R/W/HS/HC	W
Reset			0	0	0	0


Bit	7	6	5	4	3	2	1	0
		ADDR[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 31 – RIP3 Read Value of Parity bit 3

Bit 30 – RIP2 Read Value of Parity bit 2

Bit 29 – RIP1 Read Value of Parity bit 1

Bit 28 – RIP0 Read Value of Parity bit 0

Bit 27 – WIP3

Direct write of the parity bit 3 (when enabled by bit 13), readback of written data.

Bit 26 – WIP2

Direct write of the parity bit 2 (when enabled by bit 13), readback of written data.

Bit 25 – WIP1

Direct write of the parity bit 1 (when enabled by bit 13), read back of written data.

Bit 24 – WIP0

Direct write of the parity bit 0 (when enabled by bit 13), read back of written data.

Bit 22 – CMPP

Compare the contents of the addressed cache RAM line PARITY to WIP bits in this register. In READ mode, the register will return the result of the comparison.

Value	Description
1	Compare result is good.
0	Compare result has an error.

Bit 21 – EWP

Enable the four bits of parity to be directly written to the parity bits in the cache RAM.

Value	Description
1	Trigger a write of parity values from the WIP register to the cache RAM parity bits.
0	No operation.

Bit 20 – EWD

Enable four 32-bit data registers to be written to the cache.

Value	Description
1	Trigger a write of data values from the CHEDAT register to the cache RAM.
0	No operation.

Bit 19 – CMPD

Compare the contents of the addressed cache RAM line to the contents of data registers. Read and compare with the values supplied.

Note: Read operation allows cache parity hardware to be used to check for parity evaluation. In READ mode, the register will return the result of the comparison. This function will also compare the contents of the cache parity bits against the parity bits in the control registers bits 16-19 (WIPn) if the CMPP bit is enabled.

Value	Description
1	Compare result is good.
0	Compare result has an error.

Bit 18 – RD

Read/Write four 32-bit register values to address cache RAM into CHEDAT, and the four cache parity bits will be read into the RIP bits of this SFR.

Value	Description
1	Trigger a single READ event.
0	No operation.

Bit 13 – RVAL

Value read from the TAG in the addressed CACHE line.

Bit 12 – WVAL

Value written from the TAG in the addressed CACHE line.

Bit 11 – CMPV

Compare the bit in WVAL (bit 12) with the value in the current CACHE line and post the results to this bit.

Value	Description
1	Values are compared.
0	Values are not compared.

Bit 10 – WV

Write the value in the WVAL (bit 12) to the tag valid bit in the CACHE line.

Bits 6:0 – ADDR[6:0]

Address of a 128-bit, four-word cache line.