3.4.2.6 Tag Data Register
Note:
- The user software should not attempt to write to this register on the instruction cycle immediately following a read from the TAGCMD register; the write contents will be lost due to the hardware read of this register.
- The tag address is comprised of bits 23-11 of the program memory address for a 128-line direct-mapped cache.
- The tag data/address is 23 bits aligned, with unused bits (0-10 being ignored by hardware, and only bits 11-23 will be active).
| Name: | TAGDAT |
| Offset: | 0x1E80 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDR[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDR[15:11] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |