FPU Functional Block Unavailable

If the FPU pipeline is not full, and the FPU attempts to dispatch an instruction from the RD-stage that uses a functional block that is already in use by a prior instruction, an internal structural hazard will result, and the RD-stage will be stalled until such time that the functional block is no longer in use. If the CPU attempts to issue another FPU instruction before this occurs, the FPU will then stall the CPU until the hazard resolves.

This scenario can arise as a result of in-order retirement where instructions that target the same functional block will be stalled in the pipeline waiting for slower, older instructions to complete execution. An example is shown in Figure 3-34 where a slow instruction (FSIN) is followed by multiple instructions that target the same MISC_SP functional block. The first FMOV will stall in X [0] waiting for the FSIN to retire, resulting in an internal structural hazard. The subsequently issued FMOV will issue but will be stalled in the RD-stage because it cannot progress into X [0] until the first FMOV is able to move into the WB-stage, another internal structural hazard. As the RD-stage is now stalled, should the CPU attempt to issue any additional FPU FMOV or FMOVC instructions (which share the same functional block), the FPU will stall the CPU until such time that the pipeline can advance again, causing an external structural hazard.

This scenario will always arise for a sequential issue of the multi-cycle iterative FDIV instruction (all other instructions can be pipelined) as shown in Figure 3-35.