29.11.6 CLB Clock Selection

Name:	CLBCLK
Offset:	0x0515


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] CLB Clock Selection

Table 29-3. CLBCLK Clock Selections
Value	Description
`11111-10011`	Reserved
`10010`	CLKR
`10001`	SOSC
`10000`	TMR4_Postscaled_OUT
`01111`	TMR3_overflow_OUT
`01110`	TMR2_Postscaled_OUT
`01101`	TMR1_overflow_OUT
`01100`	TMR0_overflow_OUT
`01011`	ADCRC
`01010`	EXTOSC
`01001`	MFINTOSC (32 kHz)
`01000`	MFINTOSC (500 kHz)
`00111`	LFINTOSC
`00110`	HFINTOSC
`00101`	F_OSC
`00100`	CLBIN3PPS
`00011`	CLBIN2PPS
`00010`	CLBIN1PPS
`00001`	CLBIN0PPS
`00000`	CLBCLKPPS

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