29.11.1 CLB Control Register
| Name: | CLBCON |
| Offset: | 0x050C |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | DB0 | RDHOLD | BUSY | ||||||
| Access | R/W | R | R/W | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – EN CLB Software Enable
| Value | Description |
|---|---|
| 1 | CLB module is enabled |
| 0 | CLB module is disabled |
Bit 2 – DB0 CLB Debug Status
Bit 1 – RDHOLD CLBSWOUT Read Hold
| Value | Description |
|---|---|
| 1 | CLBSWOUT registers will capture the BLE output values and will remain stable |
| 0 | CLBSWOUT registers are not synchronized to the BLE outputs and is raw data |
Bit 0 – BUSY CLBSWIN Register Input Busy Status
| Value | Description |
|---|---|
| 1 | CLBSWIN registers are being synchronized and should not be changed |
| 0 | CLBSWIN registers can be written |