2.10.11.1 Timing Characteristics

The following figure shows the timing model of FIFO.

Figure 2-67. FIFO Model

The following figures show the timing waveforms of FIFO write and FIFO read.

Figure 2-68. FIFO Write Timing Waveform

Figure 2-69. FIFO Read Timing Waveform

The following tables list the timing characteristics of different FIFO blocks.

Table 2-102. One FIFO Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2Speed		–1Speed		StdSpeed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
FIFOModule Timing
t_WSU	Write setup	11.40		12.98		15.26		ns
t_WHD	Write hold	0.22		0.25		0.30		ns
t_WCKH	WCLK high	0.75		0.75		0.75		ns
t_WCKL	WCLK low	0.88		0.88		0.88		ns
t_WCKP	Minimum WCLK period	1.63		1.63		1.63		ns
t_RSU	Read setup	11.63		13.25		15.58		ns
t_RHD	Read hold	0.00		0.00		0.00		ns
t_RCKH	RCLK high	0.77		0.77		0.77		ns
t_RCKL	RCLK low	0.93		0.93		0.93		ns
t_RCKP	Minimum RCLK period	1.70		1.70		1.70		ns
t_CLRHF	Clear high	0.00		0.00		0.00		ns
t_CLR2FF	Clear-to-flag (EMPTY/FULL)	1.92		2.18		2.57		ns
t_CLR2AF	Clear-to-flag (AEMPTY/AFULL)	4.39		5.00		5.88		ns
t_CK2FF	Clock-to-flag (EMPTY/FULL)	2.13		2.42		2.85		ns
t_CK2AF	Clock-to-flag (AEMPTY/AFULL)	5.04		5.75		6.75		ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	1.32		1.51		1.77		ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	2.16		2.46		2.90		ns

Note: Timingdata for this single block FIFO has a depth of 4,096. For all other combinations, use Microchip’s timing software.

Table 2-103. Two FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2Speed		–1Speed		StdSpeed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
FIFOModule Timing
t_WSU	Write setup	13.75		15.66		18.41		ns
t_WHD	Write hold	0.00		0.00		0.00		ns
t_WCKH	WCLK high	0.75		0.75		0.75		ns
t_WCKL	WCLK low	1.76		1.76		1.76		ns
t_WCKP	Minimum WCLK period	2.51		2.51		2.51		ns
t_RSU	Read setup	14.33		16.32		19.19		ns
t_RHD	Read hold	0.00		0.00		0.00		ns
t_RCKH	RCLK high	0.73		0.73		0.73		ns
t_RCKL	RCLK low	1.89		1.89		1.89		ns
t_RCKP	Minimum RCLK period	2.62		2.62		2.62		ns
t_CLRHF	Clear high	0.00		0.00		0.00		ns
t_CLR2FF	Clear-to-flag (EMPTY/FULL)	1.92		2.18		2.57		ns
t_CLR2AF	Clear-to-flag (AEMPTY/AFULL)	4.39		5.00		5.88		ns
t_CK2FF	Clock-to-flag (EMPTY/FULL)	2.13		2.42		2.85		ns
t_CK2AF	Clock-to-flag (AEMPTY/AFULL)	5.04		5.75		6.75		ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	1.43		1.63		1.92		ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	2.26		2.58		3.03		ns

Note: Timingdata for these two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, use Microchip’s timing software.

Table 2-104. Four FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2Speed		–1Speed		StdSpeed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
FIFOModule Timing
t_WSU	Write setup	14.60		16.63		19.55		ns
t_WHD	Write hold	0.00		0.00		0.00		ns
t_WCKH	WCLK high	0.75		0.75		0.75		ns
t_WCKL	WCLK low	2.51		2.51		2.51		ns
t_WCKP	Minimum WCLK period	3.26		3.26		3.26		ns
t_RSU	Read setup	15.27		17.39		20.44		ns
t_RHD	Read hold	0.00		0.00		0.00		ns
t_RCKH	RCLK high	0.73		0.73		0.73		ns
t_RCKL	RCLK low	2.96		2.96		2.96		ns
t_RCKP	Minimum RCLK period	3.69		3.69		3.69		ns
t_CLRHF	Clear high	0.00		0.00		0.00		ns
t_CLR2FF	Clear-to-flag (EMPTY/FULL)	1.92		2.18		2.57		ns
t_CLR2AF	Clear-to-flag (AEMPTY/AFULL)	4.39		5.00		5.88		ns
t_CK2FF	Clock-to-flag (EMPTY/FULL)	2.13		2.42		2.85		ns
t_CK2AF	Clock-to-flag (AEMPTY/AFULL)	5.04		5.75		6.75		ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	2.36		2.69		3.16		ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	2.83		3.23		3.79		ns

Note: Timingdata for these four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, use Microchip’s timing software.

Table 2-105. Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2Speed		–1Speed		StdSpeed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
FIFOModule Timing
t_WSU	Write setup	15.46		17.61		20.70		ns
t_WHD	Write hold	0.00		0.00		0.00		ns
t_WCKH	WCLK high	0.75		0.75		0.75		ns
t_WCKL	WCLK low	5.13		5.13		5.13		ns
t_WCKP	Minimum WCLK period	5.88		5.88		5.88		ns
t_RSU	Read setup	16.22		18.47		21.72		ns
t_RHD	Read hold	0.00		0.00		0.00		ns
t_RCKH	RCLK high	0.73		0.73		0.73		ns
t_RCKL	RCLK low	5.77		5.77		5.77		ns
t_RCKP	Minimum RCLK period	6.50		6.50		6.50		ns
t_CLRHF	Clear high	0.00		0.00		0.00		ns
t_CLR2FF	Clear-to-flag (EMPTY/FULL)	1.92		2.18		2.57		ns
t_CLR2AF	Clear-to-flag (AEMPTY/AFULL)	4.39		5.00		5.88		ns
t_CK2FF	Clock-to-flag (EMPTY/FULL)	2.13		2.42		2.85		ns
t_CK2AF	Clock-to-flag (AEMPTY/AFULL)	5.04		5.75		6.75		ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	3.39		3.86		4.54		ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	4.93		5.62		6.61		ns

Note: Timing data for these eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, useMicrochip’s timing software.

Table 2-106. Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2Speed		–1Speed		StdSpeed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
FIFOModule Timing
t_WSU	Write setup	16.32		18.60		21.86		ns
t_WHD	Write hold	0.00		0.00		0.00		ns
t_WCKH	WCLK high	0.75		0.75		0.75		ns
t_WCKL	WCLK low	13.40		13.40		13.40		ns
t_WCKP	Minimum WCLK period	14.15		14.15		14.15		ns
t_RSU	Read setup	17.16		19.54		22.97		ns
t_RHD	Read hold	0.00		0.00		0.00		ns
t_RCKH	RCLK high	0.73		0.73		0.73		ns
t_RCKL	RCLK low	14.41		14.41		14.41		ns
t_RCKP	Minimum RCLK period	15.14		15.14		15.14		ns
t_CLRHF	Clear high	0.00		0.00		0.00		ns
t_CLR2FF	Clear-to-flag (EMPTY/FULL)	1.92		2.18		2.57		ns
t_CLR2AF	Clear-to-flag (AEMPTY/AFULL)	4.39		5.00		5.88		ns
t_CK2FF	Clock-to-flag (EMPTY/FULL)	2.13		2.42		2.85		ns
t_CK2AF	Clock-to-flag (AEMPTY/AFULL)	5.04		5.75		6.75		ns
t_RCK2RD1	RCLK-to-OUT (Pipelined)	12.08		13.76		16.17		ns
t_RCK2RD2	RCLK-to-OUT (Non-Pipelined)	12.83		14.62		17.18		ns

Note: Timing data for these sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, use Microchip’s timing software.