7 Clocking Structure

In this demo design, there are two clock domains. The on-board 122.88 MHz crystal oscillator drives the XCVR reference clock in 8b10b mode. This generates Lane0/1 RX clock and Lane0/1 TX clock. CPRI master system, CPRI slave Subsystem, and HDL modules use TX and RX clock (122.88 MHz).

The on-chip 160 MHz RC oscillator drives the CCC which generates 100 MHz clock. The UART_Interface, Mi-V system, and the AHB interface of the CPRI master subsystem and CPRI slave subsystem use 100 MHz clock. The clock divider generates 40 MHz clock for the XCVR_ERM.

The following figure shows the clocking structure in the reference design.

Figure 7-1. Clocking Structure

The following table lists the clocks used in the demo design.

Table 7-1. Clocks
Clock NameSourceFrequency
Mi-V ClockCCC_0100 MHz
RX_CLK_L0_RTransceiver RX recovered clock (Lane0)122.88 MHz
RX_CLK_L1_RTransceiver RX recovered clock (Lane1)122.88 MHz
TX_CLK_L0_RTransceiver TX PLL clock (Lane0)122.88 MHz
TX_CLK_L1_RTransceiver TX PLL clock (Lane1)122.88 MHz
CTRL_CLKCLK Divider40 MHz