5 Port Description
(Ask a Question)The following table lists the input and output ports of the design.
| Signal | Direction | Description |
|---|---|---|
| RESETN | Input | External reset |
| REF_CLK_PAD_P and REF_CLK_PAD_N | Input | This is the differential reference clock generated from the on-board 122.88 MHz oscillator |
| LANE0_RXD_P and LANE0_RXD_N | Input | Transceiver Receiver differential input of Lane0 |
| LANE1_RXD_P and LANE1_RXD_N | Input | Transceiver Receiver differential input of Lane1 |
| RX | Input | This is the input signal received by the UART interface from the GUI |
| LANE0_TXD_P and LANE0_TXD_N | Output | Transceiver Receiver differential output of Lane0 |
| LANE1_TXD_P and LANE1_TXD_N | Output | Transceiver Receiver differential output of Lane1 |
| Config_done | Output | Indicates CPRI master and slave register configuration is completed by Mi-V processor |
| VSS_lock | Output | Indicates the Received Vendor specific data is correct |
| Ethernet_lock | Output | Indicates the Received Ethernet data is correct |
| AxC_Control_lock | Output | Indicates the received Antenna Control data is correct |
| AxC_Data_lock | Output | Indicates the received Antenna IQ data is correct |
| TX | Output | This is the output data received by the GUI from the UART interface |