13 Appendix 3: References

This section lists the documents that provide more information about the concepts and features covered in this demo guide.

• For more information about PolarFire transceiver blocks, see PolarFire Family Transceiver User Guide .
• For more information about Libero, ModelSim, and Synplify, see Libero SoC v12.0 and later .
• For more information about CPRI IP, see Libero Catalog > Solution-Wireless > Microchip CPRI User Guide.
• For more information about PolarFire Evaluation kit, see UG0747: PolarFire FPGA Evaluation Kit User Guide .
• For more information about Power-Up and Reset, see PolarFire Family Power-Up and Resets User Guide .
• For more information about the CoreJTAGDEBUG IP core, see CoreJTAGDebug from Libero > Catalog.
• For more information about the MIV_RV32 IP core, see MIV_RV32 from the Libero SoC Catalog.
• For more information about the CoreUARTapb IP core, see CoreUARTapb.
• For more information about the CoreAHBLite IP core, see CoreAHBLite.
• For more information about the CoreAPB3 IP core, see CoreAPB3.
• For more information about the CoreGPIO IP core, see CoreGPIO.