4 Demo Design

The PolarFire CPRI Loopback demo design is developed for demonstrating CPRI IP in Slave mode. The pattern generator in this demo design generates CPRI protocol data such as IQ data, VSS data, Ethernet data, and Antenna carrier control data which is provided to the CPRI master module. The CPRI master module frames the data according to the CPRI protocol. The generated frames from the CPRI master are loopbacked to CPRI slave IP using the XCVR. The CPRI slave IP unpacks the incoming data into IQ data, VSS data, Ethernet data, and Antenna carrier control data. This data is then loopbacked from CPRI slave IP to CPRI master module, therefore demonstrates Full duplex transmission of CPRI IP in Slave mode.

The following figure shows the top-level block diagram of the CPRI demo design.

Figure 4-1. CPRI Demo Design Block Diagram
The following steps describe the data flow in the demo design:
  1. The Mi_V_module configures the registers of the CPRI Master module and CPRI slave IP blocks.
  2. The reference design uses a transceiver interface (PF_XCVR_ERM) configured in 8b10b mode running at 4.9152 Gbps data rate, 32-bit PCS fabric interface, and 122.88 MHz reference clock.
  3. The CPRI master module and CPRI IP are configured at Line Rate 5: 4.9152 Gbps with four Antenna carriers.
  4. The CPRI master module receives the IQ data from the TX IQ Data Generator and control information such as Ethernet data, Vendor specific data, and Antenna carrier control from the respective pattern generators.
  5. CPRI master module then frames the incoming data and transmits a 32-bit CPRI frame to the transceiver.
  6. The differential serial data of TX and RX is looped back using an on-board loopback.
  7. The CPRI slave IP receives the incoming frames and segregates the incoming data according to the CPRI protocol.
  8. The segregated IQ data, Vendor specific data, Ethernet data, and Antenna carrier control information are written to the respective loop back FIFO’s.
  9. CPRI slave IP then reads the data from loopback FIFO's frames the data and transmits the a 32-bit CPRI frame to CPRI master module through the transceiver.
  10. The CPRI master module receives the incoming frames, segregates and sends the incoming data to respective pattern checkers.
  11. Incoming control information is compared with the control data for Vendor specific, Fast Ethernet, IQ data, and Antenna carrier control data. When the data is matched, the respective lock signals are asserted.
  12. The IQ data and control information such as Ethernet, Vendor specific, and Antenna carrier control lock signals from CPRI slave IP and master module along with transceiver RX_Valid and RX_ready for both the lanes are sent to the UART_interface block.
  13. The UART_interface block forwards these status signal and locks information on its TX interface to the GUI for display.