1 Common Public Radio Interface Demo

CPRI IP cores are easy to integrate with CPRI-based data converters to develop high-bandwidth applications. Microchip® CPRI IP supports from Line Rate 1 (614.4 Mbps) to Line Rate 7 (9830.4 Mbps). The transceiver supports link rate from 250 Mbps to 12.5 Gbps per lane. The transceiver supports up to Line Rate 9 for CPRI protocol. The transceiver (PF_XCVR) module integrates several functional blocks to support multiple high-speed serial protocols within the FPGA.

Figure 1-1. Radio Base Station System

This demo design is created using the PolarFire® high-speed transceiver blocks and CPRI Slave IP core. The design operates in the loopback mode by sending the CPRI Master data to the CPRI Slave IP core through the transceiver lanes, which are looped back on the board. This loopback setup facilitates a stand-alone CPRI interface demo that does not require CPRI testers and other devices to validate the design.

The demo design shows CPRI loopback using transceiver on the evaluation board. The CPRI Slave IP is configured with the following settings:

  • Line Rate 5: 4.9152 Gbps
  • Number of Antenna carriers: 4
  • The transceiver is configured in 8b10b mode running at 4.9152 Gbps data-rate
  • 32-bit PCS fabric interface using a 122.88 MHz reference clock