32.3.3.2 Output

The TCB peripheral synchronization and output logic level depend on the selected Timer Mode (CNTMODE) bit field in the Control B (TCBn.CTRLB) register. In the Single-Shot mode, the peripheral can be configured so that the signal generation happens asynchronously to an incoming event by writing a ‘1’ to the Asynchronous Enable (ASYNC) bit in the Control B (TCBn.CTRLB) register. Then, the output signal is set immediately at the incoming event instead of being synchronized to the TCB clock. Due to the synchronization delay for the counter, the waveform output will be set high for three to four CLK_TCB cycles more than what is defined by the TOP value.

Writing a ‘1’ to the Capture/Compare Output Enable (CCMPEN) bit in the Control B (TCBn.CTRLB) register enables and makes the waveform output available on the corresponding pin, overriding the value in the corresponding PORT output register.

The table below lists the different configurations and their impact on the output.

Table 32-2. Output Configuration
CCMPEN	CNTMODE	ASYNC	Output
`1`	Single-Shot mode	`0`	The output is high when the counter starts and low when the counter stops
	Single-Shot mode	`1`	The output is high when the event arrives and low when the counter stops
	8-bit PWM mode	Not applicable	8-bit PWM mode
	Other modes	Not applicable	The output is static as configured in the Capture/Compare Pin Initial Value (CCMPINIT) bit in the Control B (TCBn.CTRLB) register.
`0`	Not applicable	Not applicable	No output

Changing modes while the peripheral is enabled is not recommended, as this can produce an unpredictable output. An interrupt flag may be set during the timer configuration. Clearing the TCB Interrupt Flags (TCBn.INTFLAGS) register is recommended after configuring this peripheral.