17.2 Overview

The RAM Controller (RAMCTRL) interfaces the data bus to internal RAM. SEC-DED ECC and bus parity logic are incorporated into the hardware for improved data integrity with error injection capabilities for latent fault detection.

The ECC logic generates and stores ECC parity data for each write operation to RAM. The ECC parity data are automatically checked using a dual lockstep checker for additional redundancy on each RAM read. Single faults are automatically corrected, while single faults and double faults are reported to the Error Controller (ERRCTRL).

The bus checks the integrity of address, data, and control signals on every RAM data read and write using mechanisms such as parity and redundancy. Integrity errors are reported to ERRCTRL.

Both the ECC and bus parity logic support the intentional provocation of errors through an error injection register interface, allowing verification that errors can be detected as expected.

RAMCTRL is always enabled.