5.1 I/O Multiplexing


VQFN32/ TQFP32	SOIC28/SSOP28/ SPDIP28	VQFN28	SOIC20	Pin name^(1,2)	Special	ADCn	ACn	DAC0	ZCDn	USARTn	SPIn	TWIn⁽⁴⁾	TCAn	TCBn	TCD0	EVSYS	CCL-LUTn	ERRCTRL
30	22	26	4	PA0	XTALHF1 EXTCLK					0, TxD	0, MOSI⁽³⁾	0, SDA(HC)⁽³⁾	0, WO0				0, IN0
31	23	27	5	PA1	XTALHF2					0, RxD	0, MISO⁽³⁾	0, SCL(HC)⁽³⁾	0, WO1				0, IN1
32	24	28	6	PA2		AIN22				0, XCK 0, TxD⁽³⁾		0, SDA(HC)	0, WO2	0, WO		EVOUTA	0, IN2	HEART
1	25	1	7	PA3		AIN23				0, XDIR 0, RxD⁽³⁾		0, SCL(HC)	0, WO3	1, WO			0, OUT
2	26	2	8	PA4		AIN24				0, TxD⁽³⁾	0, MOSI		0, WO4		WOA			HEART⁽³⁾
3	27	3	9	PA5		AIN25				0, RxD⁽³⁾	0, MISO		0, WO5		WOB
4	28	4	10	PA6		AIN26				0, XCK⁽³⁾	0, SCK				WOC		0, OUT⁽³⁾	HEART⁽³⁾
5	1	5	11	PA7	CLKOUT	AIN27	0, OUT 1, OUT 2, OUT		0, OUT⁽⁵⁾ 3, OUT	0, XDIR⁽³⁾	0, SS				WOD	EVOUTA⁽³⁾		HEART⁽³⁾
6	2	6	-	PC0		AIN28				1, TxD	1, MOSI 0, MOSI⁽³⁾ 0, SCK⁽³⁾		0, WO0⁽³⁾	2, WO			1, IN0
7	3	7	12	PC1		AIN29				1, RxD 0, TxD⁽³⁾	1, MISO 0, MISO⁽³⁾ 0, SS⁽³⁾ 0, MOSI⁽³⁾		0, WO1⁽³⁾	3, WO⁽³⁾			1, IN1
8	4	8	13	PC2		AIN30	0, AINN3 1, AINN3		3, ZCIN	1, XCK 0, RxD⁽³⁾	1, SCK 0, SCK⁽³⁾ 0, MISO⁽³⁾	0, SDA(C) 0, SDA(HC)⁽³⁾	0, WO2⁽³⁾			EVOUTC	1, IN2
9	5	9	14	PC3	TWI Fm+	AIN31	0, AINP4 1, AINP4			1, XDIR 0, XCK⁽³⁾	1, SS 0, SS⁽³⁾ 0, SCK⁽³⁾	0, SCL(C) 0, SCL(HC)⁽³⁾	0, WO3⁽³⁾				1, OUT
10	6	10	15	VDDIO2
-	-	-	-	GND
11	7	11	-	PD1		AIN1			0, ZCIN				0, WO1⁽³⁾				2, IN1
12	8	12	-	PD2		AIN2	0, AINP0 1, AINP0 2, AINP0						0, WO2⁽³⁾			EVOUTD	2, IN2
13	9	13	-	PD3		AIN3	0, AINN0 1, AINP1						0, WO3⁽³⁾				2, OUT
14	10	14	16	PD4	VREFB	AIN4	1, AINP2 2, AINP1			0, TxD⁽³⁾	0, MOSI⁽³⁾		0, WO4⁽³⁾		WOC⁽³⁾			HEART⁽³⁾
15	11	15	17	PD5		AIN5	1, AINN0			0, RxD⁽³⁾	0, MISO⁽³⁾		0, WO5⁽³⁾		WOD⁽³⁾
16	12	16	18	PD6		AIN6	0, AINP3 1, AINP3 2, AINP3	OUT		0, XCK⁽³⁾ 1, TxD⁽³⁾	0, SCK⁽³⁾						2, OUT⁽³⁾
17	13	17	19	PD7	VREFA	AIN7	0, AINN2 1, AINN2 2, AINN0/AINN2			0, XDIR⁽³⁾ 1, RxD⁽³⁾	0, SS⁽³⁾					EVOUTD⁽³⁾
18	14	18	20	VDD
19	15	19	1	GND
20	16	20	-	PF0	XTAL32K1	AIN16				2, TxD			0, WO0⁽³⁾		WOA⁽³⁾		3, IN0
21	17	21	-	PF1	XTAL32K2	AIN17				2, RxD			0, WO1⁽³⁾		WOB⁽³⁾		3, IN1
22	-	-	-	PF2		AIN18				2, XCK		1, SDA(HC)	0, WO2⁽³⁾		WOC⁽³⁾	EVOUTF	3, IN2
23	-	-	-	PF3		AIN19				2, XDIR		1, SCL(HC)	0, WO3⁽³⁾		WOD⁽³⁾		3, OUT
24	-	-	-	PF4		AIN20				2, TxD⁽³⁾			0, WO4⁽³⁾	0, WO⁽³⁾
25	-	-	-	PF5		AIN21				2, RxD⁽³⁾			0, WO5⁽³⁾	1, WO⁽³⁾				HEART⁽³⁾
26	18	22	2	RESET	RESET
27	19	23	3	UPDI	UPDI
28	20	24	-	VDD
29	21	25	-	GND

Note:

Pin names are of type Pxn, with x being the PORT instance (A, B, C, ...) and n the pin number. Notation for signals is PORTx_PINn. All pins can be used as event inputs.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternative pin positions. To select alternative pin positions, refer to the Port Multiplexer section.
TWI pins are marked HC if they can be used as TWI Host or Client pins and C if they can only be used as TWI Client pins.
Devices with 20 pins provide ZCD3 only.