11.2 Overview

The bus controller handles all access on the data buses, acting as the main interface between the initiators and target buses.

The bus matrix executes any data transfers from the requesting initiators to the selected bus targets. The bus targets can respond to a transfer request by either completing the access or ignoring the access and returning a Bus Error signal. This signal is returned to the bus initiator and handled in a bus-initiator-specific way, usually by discarding the transfer and setting an interrupt flag in the bus initiator.

Parity and other redundancy and consistency checks protect the data bus signal integrity to detect random errors occurring on the data bus. Both data bus initiators and data bus targets can detect parity errors and other data bus consistency errors. Detection of bus-related errors happens in an initiator- or target-specific way, usually by discarding the transfer and setting a bus error interrupt flag in the initiator. Refer to the data sheet of the respective initiator and target for information on how bus errors are handled.

The bus controller handles address decoding and bus arbitration for all the initiators in the system. An unlimited number of initiators and targets is supported, but some restrictions apply. Two initiators can access different target buses at the same time. The arbiter will take action only when a conflict occurs. This bus section is called the high-speed bus. Low-bandwidth peripherals and interfaces are connected to an I/O bus bridge. Only one transfer can be active on the I/O bus at a time. The USART and timers are examples of peripherals connected to the I/O bus. Due to only facilitating one connection at a time, this section is regarded as low-speed.