45.10.5 Sigma-Delta Analog-to-Digital Converter (SDADC) Characteristics

Table 45-26. Operating Conditions⁽¹⁾
Symbol	Parameters	Conditions		Min.	Typ.	Max.	Unit
Res	Resolution	Differential mode		-	16	-	bits
Res	Resolution	Single-Ended mode ⁽³⁾		-	15	-	bits
CLK_SDADC	Sampling Clock Speed	-		1	-	6	MHz
CLK_SDADC_FS	Conversion rate	-		CLK_SDADC/4
fs	Output Data Rate	Free Running mode		CLK_SDADC_FS / OSR
fs	Output Data Rate	Single Conversion mode SKPCNT = N		(CLK_SDADC_FS / OSR) x (N+1)
OSR	Oversampling ratio	Differential mode		64	256	1024	Cycles
Vin	Input Conversion range	VREF<VDDANA-0.3V	Differential mode Gaincorr = 0x1	- VREF	-	VREF	V
		VREF<VDDANA-0.3V	Single-Ended mode Gaincorr = 0x1⁽³⁾	0	-	VREF	V
		VREF> = VDDANA-0.3V	Differential mode Gaincorr = 0x1	-0.7xVREF	-	0.7xVREF	V
		VREF> = VDDANA-0.3V	Single-Ended mode Gaincorr = 0x1⁽³⁾	0	-	0.7xVREF	V
Vref	Reference Voltage range			1	-	VDDANA	V
Vcom	Common mode voltage	Differential mode		0	-	VDDANA	V
Cin	Input capacitance			0.425	0.5	0.575	pF
Zin	Input impedance	Differential mode		1/(Cin x CLK_SDADC_FS)			kΩ
Zin	Input impedance	Single-Ended mode ⁽³⁾		1/(Cin x CLK_SDADC_FS x 2)			kΩ
	Input anti-alias filter recommendation⁽²⁾	Rext		-	1.0	-	kΩ
	Input anti-alias filter recommendation⁽²⁾	Cext		3.3	-	10	nF

Note:

These values are based on simulation and not covered by test or characterization.
External anti-alias filter must be placed in front of each SDADC input to ensure high-frequency signals to not alias into measurement bandwidth. Use capacitors of X5R type for DC measurement, or capacitors of COG or NPO type for AC measurement.
This mode corresponds to a differential mode where the selected AINNx pin is externally grounded.

Table 45-27. SDADC DC Performance: Differential Input Mode ⁽¹⁾⁽²⁾
Symbol	Parameters	Conditions (2)	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity	CLK_SDADC = 6MHz; VREF = 1.2V	-	+/-1.3	+/-2	LSB
INL	Integral Non Linearity	CLK_SDADC = 6MHz; INT VREF = 5.5V	-	+/-5.3	+/-11	LSB
DNL	Differential Non Linearity	CLK_SDADC = 6MHz; VREF = 1.2V	-	+1.4/-1	+1.3/-1	LSB
DNL	Differential Non Linearity	CLK_SDADC = 6MHz; INT VREF = 5.5V	-	+2.1/-1	+1.7/-1	LSB
Off	Offset Error	CLK_SDADC = 6MHz; VREF = 1.2V	-	+/-0.6	+/-3	mV
Off	Offset Error	CLK_SDADC = 6MHz; INT VREF = 5.5V	-	+/-3.9	+/-6	mV
Tco	Offset Error Drift	CLK_SDADC = 6MHz; VREF = 1.2V	2.3	3.6	5.0	uV/°C
Eg	Gain Errors	CLK_SDADC = 6MHz; VREF = 1.2V	-	+/-1.1	+/-3.7	%
Eg	Gain Errors	CLK_SDADC = 6MHz; INT VREF = 5.5V	-	+/-1.1	+/-3.4	%
TCg	Gain Drift	CLK_SDADC = 6MHz; VREF = 1.2V	-10.9	1.2	7.6	ppm/°C
Input noise rms	AC Input noise rms	OSR = 256	-	0.08	0.12	mVrms

Note:

These values are based on characterization.
OSR = 256, Chopper ON.

Table 45-28. SDADC AC Performance: : Differential Input Mode⁽¹⁾
Symbol	Parameters	Conditions (2)	Min.	Typ.	Max.	Unit
ENOB	Effective Number Of Bits	Ext ref = 1.2V	13.5	14.2	14.4	bits
ENOB	Effective Number Of Bits	Int Ref = 5.5V	11	11.2	11.4	bits
DR	Dynamic Range	Ext ref = 1.2V	89	91	92	dB
DR	Dynamic Range	Int Ref = 5.5V	83	92	96	dB
SNR	Signal to Noise Ratio	Ext ref = 1.2V	84	88	89	dB
SNR	Signal to Noise Ratio	Int Ref = 5.5V	77	79	80	dB
SINAD	Signal to Noise + Distortion Ratio	Ext ref = 1.2V	83	87	89	dB
SINAD	Signal to Noise + Distortion Ratio	Int Ref = 5.5V	68	69	71	dB
THD	Total Harmonic Distortion	Ext ref = 1.2V	-105	-100	-92	dB
THD	Total Harmonic Distortion	Int Ref = 5.5V	-70	-69	-69	dB

Note:

These values are based on characterization.
OSR = 256, Fs = 6 MHz, Fin = 13 kHz.

Table 45-29. Power consumption ⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max.	Units
IDD VDDANA	Power consumption	CTLSDADC = 0x0 External Ref - VDDANA = 5.5V Vref = 2V Ref buf on SCLK_SDADC = 6 MHz	Max 85°C Typ 25°C	644	695	μA
IDD VDDANA	Power consumption	CTLSDADC = 0x0 Internal Ref - VDDANA = Vref = 5.5V Ref buf off SCLK_SDADC = 6 MHz	Max 85°C Typ 25°C	605	636	μA

Note:

These are based on characterization.