48.6.3 Sigma-Delta Analog-to-Digital Converter (SDADC) Characteristics

Table 48-10. SDADC DC Performance: Differential Input Mode, Chopper ON ⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ.	Max.	Unit
INL	Integral Non Linearity	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-2.9	+/-4.1	LSB
INL	Integral Non Linearity	CLK_SDADC = 3 MHz, INT VREF = 5.5V	-	+/-8.4	+/-9.3	LSB
DNL	Differential Non Linearity	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+1.5/-1	+2.2/-1	LSB
DNL	Differential Non Linearity	CLK_SDADC = 3 MHz, INT VREF = 5.5V	-	+2.1/-1	+2.9/-1	LSB
Eg	Gain Errors	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-0.7	+/-2.4	%
Eg	Gain Errors	CLK_SDADC = 3 MHz, INT VREF = 5.5V	-	+/-0.9	+/-2.2	%
TCg	Gain Drift	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-6.9	4.4	17.5	ppm/°C
Off	Offset Error	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-3.1	+/-10.7	mV
Off	Offset Error	CLK_SDADC = 3 MHz, INT VREF = 5.5V	-	+/-0.5	+/-3.3	mV
Tco	Offset Error Drift	CLK_SDADC = 3 MHz, VREF = 1.2V, VDDANA = 2.7V	-1.5	-0.1	1.2	µV/°C

Note:

OSR = 256

Table 48-11. SDADC DC Performance: Differential Input Mode, Chopper OFF ⁽¹⁾
Symbol	Parameters	Conditions	Min.	Typ	Max.	Unit
INL	Integral Non Linearity	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-5.5	+/-10.2	LSB
INL	Integral Non Linearity	CLK_SDADC = 6 MHz, INT VREF = 5.5V	-	+/-8.9	+/-10.8	LSB
DNL	Differential Non Linearity	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+2.8/-1	+4.1/-1	LSB
DNL	Differential Non Linearity	CLK_SDADC = 6 MHz, INT VREF = 5.5V	-	+2.5/-1	+4.8/-1	LSB
Eg	Gain Errors	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-0.7	+/-3.1	%
Eg	Gain Errors	CLK_SDADC = 6 MHz, INT VREF = 5.5V	-	+/-0.9	+/-2.2	%
TCg	Gain Drift	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-19.7	5.2	20.9	ppm/°C
Off	Offset Error	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-	+/-2.2	+/-21.2	mV
Off	Offset Error	CLK_SDADC = 6 MHz, INT VREF = 5.5V	-	+/-4.9	+/-25.7	mV
Tco	Offset Error Drift	CLK_SDADC = 6 MHz, VREF = 1.2V, VDDANA = 2.7V	-14.2	12.4	60	µV/°C
Input noise rms	AC Input noise rms	OSR = 256, VREF = 1.2V, VDDANA = 2.7V	-	19	20	µVrms
Input noise rms	AC Input noise rms	OSR = 256, VREF = 5.5V	-	59	76	µVrms

Note:

OSR = 256

Table 48-12. SDADC AC Performance: Differential Input Mode ⁽¹⁾
Symbol	Parameters	Conditions ⁽²⁾	Min.	Typ.	Max.	Unit
ENOB	Effective Number Of Bits	Ext ref = 1.2V, VDDANA = 2.7V	12	14.2	-	bit
ENOB	Effective Number Of Bits	Int Ref = 5.5V	11	11.2	-	bit
DR	Dynamic Range	Ext ref = 1.2V, VDDANA = 2.7V	89.0	91.0	-	dB
DR	Dynamic Range	Int Ref = 5.5V	83.0	92.0	-	dB
SNR	Signal to Noise Ratio	Ext ref = 1.2V, VDDANA = 2.7V	68.7	88	-	dB
SNR	Signal to Noise Ratio	Int Ref = 5.5V	77	79	-	dB
SINAD	Signal to Noise + Distortion Ratio	Ext ref = 1.2V, VDDANA = 2.7V	73.9	87	-	dB
SINAD	Signal to Noise + Distortion Ratio	Int Ref = 5.5V	68	69	-	dB
THD	Total Harmonic Distortion	Ext ref = 1.2V, VDDANA = 2.7V	-	-94.6	-74.4	dB
THD	Total Harmonic Distortion	Int Ref = 5.5V	-	-69	-68	dB

Note:

These values are based on characterization.
OSR = 256, Chopper OFF, Sampling Clock Speed at 6Mhz, Fin = 13 kHz.

Table 48-13. Power Consumption ⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max.	Units
IDD VDDANA	Power consumption	CTLSDADC = 0x0 External Ref - VDDANA = 5.5V, VREF = 2V Ref buf on SCLK_SDADC = 6 MHz	Max 125°C Typ 25°C	644	764	uA
IDD VDDANA	Power consumption	CTLSDADC=0x0 Internal Ref - VDDANA = VREF = 5.5V Ref buf off SCLK_SDADC = 6 MHz	Max 125°C Typ 25°C	605	696	uA

Note:

These values are based on characterization.

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