45.12.3 Digital Phase Locked Loop (DPLL) Characteristics

Table 45-52. Fractional Digital Phase Locked Loop Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN⁽¹⁾	Input frequency		32		2000	KHz
f_OUT⁽¹⁾	DCO Output frequency		48		96	MHz
Jp⁽²⁾	Period jitter (Peak-Peak value)	f_IN = 32 kHz, f_OUT = 48 MHz	-	1.5	3.0	%
		f_IN= 32 kHz, f_OUT = 64 MHz	-	1.7	4.0
		f_IN= 32 kHz, f_OUT = 96 MHz	-	2.7	8.0
		f_IN= 2 MHz, f_OUT = 48 MHz	-	1.8	4.0
		f_IN= 2 MHz, f_OUT = 64 MHz	-	1.9	4.0
		f_IN= 2 MHz, f_OUT = 96 MHz	-	2.5	6.0
t_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal. f_IN = 32 kHz, f_OUT = 96 MHz	-	1.1	1.5	ms
t_LOCK⁽²⁾	Lock Time	After startup, time to get lock signal. f_IN = 2 MHz, f_OUT = 96 MHz	-	25	35	μs
Duty⁽¹⁾	Duty cycle	-	-	50	-	%

These values are based on simulation, and are not covered by test limits in production or characterization.
These values are based on characterization.
DPLL jitter is sensitive to digital on-chip activity, which is application dependent.

Table 45-53. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max.	Units
IDD	Current Consumption	Ck = 48 MHz, VDD = 5.0V	Max 85°C Typ 25°C	536	612	µA
		Ck = 64 MHz, VDD = 5.0V		640	721
		Ck = 96 MHz, VDD = 5.0V		865	970