10.4.2.2 Generic Clock Generators

Each Generic Clock Generator (GCLK_GEN[n]) can be set to run from one of six different clock sources, except for GCLK_GEN[1], which can be set to run from one of five clock sources. GCLK_GEN[1] is the only Generator that can be selected as a clock source for other Generators.

Each generator GCLK_GEN[n] can be connected to its corresponding GCLK_IO[n] pin. The GCLK_IO[n] pins can be configured either to act as a source for GCLK_GEN[n] or to output the clock signal generated by GCLK_GEN[n].

The selected source can be divided, and each Generator can be enabled or disabled independently.

Each GCLK_GEN[n] clock signal can be used as a clock source for Peripheral Channels. Each Generator output can be allocated to one or more Peripherals.

GCLK_GEN[0] is used as the clock source (GCLK_MAIN) for the synchronous clock controller inside the Main Clock. Refer to the MCLK - Main Clock Controller description for details on the synchronous clock generation. The default clock source for GCLK_GEN[0] is OSCHF divided by six, i.e. 4 MHz (after successful device initialization).