10.4.2.2.3 Changing the Clock Frequency and Duty Cycle

The selected clock source for a Generator can be divided by writing to the Division Factor bit field of the Generator Control register (GENCTRL[n].DIV). The actual division factor is determined by the divide selection bit of the GENCTRL[n] register (GENCTRL[n].DIVSEL).

When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing ‘1’ to the improve duty cycle bit of the GENCTRL[n] register (GENCTRL[n].IDC) will result in a 50/50 duty cycle.

The resulting clock frequency f_GCLK is calculated as follows:

If GENCTRL[n].DIVSEL = ' 0’ and GENCTRL[n].DIV is either ‘0x0’ or ‘0x1’, the output clock will not be divided
If GENCTRL[n].DIVSEL is ‘0’ then the resulting frequency of the GCLK is calculated as follows:
$f_{G C L K} = \frac{G E N C T R L n . S R C}{D I V}$
- If GENCTRL[n].DIV is an odd number, the Improve Duty Cycle bit of the GENCTRL[n] register (GENCTRL[n].IDC) must be set to ‘1’
- If GENCTRL[n].DIV is an even number, the GENCTRL[n].IDC bit must be ‘0’
If GENCTRL[n].DIVSEL is ‘1’ then the resulting frequency of the GCLK is calculated as follows:
$f_{G C L K} = \frac{G E N C T R L n . S R C}{2^{(D I V + 1)}}$
- GENCTRL[n].IDC must always be ‘0’

The following table shows the number of divider bits associated with each Generator:

Table 10-2. Generator Selection Overview
Value	Description	Enabled at Reset?	Divider bits (GENCTRLn.DIV)
`0x0`	Generator 0	Yes	8
`0x1`	Generator 1	No	16
`0x2`	Generator 2	No	8
`0x3`	Generator 3	No	8
`0x4 - 0xf`	Reserved	-	-

Note: The size of the DIV bit field may vary from Generator to Generator.