10.4.2.4 Synchronization

Since the Main Clock (MCLK) domain and the Peripheral Clock (GCLK_PERIPH) domains are not synchronous, some registers must be synchronized when accessed.

An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRL[n].CHEN). When changing this bit, the bit value must be read back to ensure that the synchronization is complete and to ensure glitch-free internal operation.
Note: Changing the CHEN bit value during ongoing synchronization will not generate an error.
The following registers are synchronized when written:
  • The Generic Clock Generator Control register (GENCTRL[n])
  • The Control A register (CTRLA)

Required write synchronization is denoted by the “Write Synchronized” property in the register description.