11.6.5 AHB Bridge Mask
| Name: | AHBMASK |
| Offset: | 0x10 |
| Reset: | 0x000003FF |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BROM | PAC | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMAC | HSRAM | NVMCTRL | HMATRIXHS | DSU | APBC | APBB | APBA | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 9 – BROM Boot ROM AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the Boot ROM is disabled |
| 1 | The AHB clock for the Boot ROM is enabled |
Bit 8 – PAC PAC AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the Peripheral Access Controller peripheral (CLK_PAC_AHB) is disabled |
| 1 | CLK_PAC_AHB is enabled |
Bit 7 – DMAC DMAC AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the Direct Memory Access Controller peripheral (CLK_DMAC_AHB) is disabled |
| 1 | CLK_DMAC_AHB is enabled |
Bit 6 – HSRAM HSRAM AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the High speed RAM (HSRAM) is disabled |
| 1 | The AHB clock for the HSRAM is enabled |
Bit 5 – NVMCTRL NVMCTRL AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the Non-Volatile Memory Controller peripheral (CLK_NVMCTRL_AHB) is disabled |
| 1 | CLK_NVMCTRL_AHB is enabled |
Bit 4 – HMATRIXHS HMATRIXHS AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the High-Speed Bus System (HMATRIXHS) is disabled |
| 1 | The AHB clock for the HMATRIXHS is enabled |
Bit 3 – DSU DSU AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the Device Service Unit peripheral (CLK_DSU_AHB) is disabled |
| 1 | CLK_DSU_AHB is enabled |
Bit 2 – APBC APB Bridge C AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APB Bridge C is disabled |
| 1 | The AHB clock for the APB Bridge C is enabled |
Bit 1 – APBB APB Bridge B AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APB Bridge B is disabled |
| 1 | The AHB clock for the APB Bridge B is enabled |
Bit 0 – APBA APB Bridge A AHB Clock Enable
| Value | Description |
|---|---|
| 0 | The AHB clock for the APB Bridge A is disabled |
| 1 | The AHB clock for the APB Bridge A is enabled |