11.6.8 APB Bridge C Mask
| Name: | APBCMASK |
| Offset: | 0x1C |
| Reset: | 0x00000800 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SYSCTRL | PTC | CCL | AC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADC0 | TCC0 | TC2 | TC1 | TC0 | SERCOM1 | SERCOM0 | EVSYS | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 11 – SYSCTRL SYSCTRL APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the System Controller (SYSCTRL) is disabled |
| 1 | The APB clock for the SYSCTRL is enabled |
Bit 10 – PTC PTC APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Peripheral Touch Controller peripheral (CLK_PTC_APB) is disabled |
| 1 | CLK_PTC_APB is enabled |
Bit 9 – CCL CCL APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Configurable Custom Logic peripheral (CLK_CCL_APB) is disabled |
| 1 | CLK_CCL_APB is enabled |
Bit 8 – AC AC APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Analog Comparator peripheral (CLK_AC_APB) is disabled |
| 1 | CLK_AC_APB is enabled |
Bit 7 – ADC0 ADC0 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the ADC0 instance of the Analog-to-Digital Converter peripheral (CLK_ADC0_APB) is disabled |
| 1 | CLK_ADC0_APB is enabled |
Bit 6 – TCC0 TCC0 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the TCC0 instance of the Timer/Counter for Control Applications peripheral (CLK_TCC0_APB) is disabled |
| 1 | CLK_TCC0_APB is enabled |
Bit 5 – TC2 TC2 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the TC2 instance of the Timer/Counter peripheral (CLK_TC2_APB) is disabled |
| 1 | CLK_TC2_APB is enabled |
Bit 4 – TC1 TC1 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the TC1 instance of the Timer/Counter peripheral (CLK_TC1_APB) is disabled |
| 1 | CLK_TC1_APB is enabled |
Bit 3 – TC0 TC0 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the TC0 instance of the Timer/Counter peripheral (CLK_TC0_APB) is disabled |
| 1 | CLK_TC0_APB is enabled |
Bit 2 – SERCOM1 SERCOM1 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the SERCOM1 instance of the Serial Communication Interface peripheral (CLK_SERCOM1_APB) is disabled |
| 1 | CLK_SERCOM1_APB is enabled |
Bit 1 – SERCOM0 SERCOM0 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the SERCOM0 instance of the Serial Communication Interface peripheral (CLK_SERCOM0_APB) is disabled |
| 1 | CLK_SERCOM0_APB is enabled |
Bit 0 – EVSYS EVSYS APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Event System peripheral (CLK_EVSYS_APB) is disabled |
| 1 | CLK_EVSYS_APB is enabled |