11.6.3 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x03 |
| Reset: | 0x01 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CKRDY | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
Bit 0 – CKRDY Clock Ready Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when the synchronous CPU, AHBx and APBx clocks have frequencies as
set in the CPU Clock Division (CPUDIV) register. If INTENCLR.CKRDY or INTENSET.CKRDY
is set to ‘1’, an interrupt will be generated.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Clock Ready interrupt flag.