11.6.7 APB Bridge B Mask
| Name: | APBBMASK |
| Offset: | 0x18 |
| Reset: | 0x00000027 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HMATRIXHS | MTB | DMAC | NVMCTRL | DSU | PORT | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 1 | 1 | 1 |
Bit 5 – HMATRIXHS HMATRIXHS APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the High-Speed Bus System (HMATRIXHS) is disabled |
| 1 | The APB clock for the HMATRIXHS is enabled |
Bit 4 – MTB MTB APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Micro Trace Buffer (MTB) is disabled |
| 1 | The APB clock for the MTB is enabled |
Bit 3 – DMAC DMAC APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Direct Memory Access Controller peripheral (CLK_DMAC_APB) is disabled |
| 1 | CLK_DMAC_APB is enabled |
Bit 2 – NVMCTRL NVMCTRL APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Non-Volatile Memory Controller peripheral (CLK_NVMCTRL_APB) is disabled |
| 1 | CLK_NVMCTRL_APB is enabled |
Bit 1 – DSU DSU APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the Device Service Unit peripheral (CLK_DSU_APB) is disabled |
| 1 | CLK_DSU_APB is enabled |
Bit 0 – PORT PORT APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APB clock for the I/O Pin Controller peripheral (CLK_PORT_APB) is disabled |
| 1 | CLK_PORT_APB is enabled |