11.4.2.3 Selecting the Synchronous Clock Division Ratio

The main clock, GCLK_MAIN, feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock domain by writing to the CPU Clock Division (CPUDIV) register, resulting in a CPU clock domain frequency determined by the following equation:

f_{C P U} = \frac{f_{m a i n}}{C P U D I V}

If the application attempts to write forbidden values in the CPUDIV register, the register is written, but these invalid values are not used. Additionally, a violation is reported to the Peripheral Access Controller (PAC) peripheral.

The CPUDIV register can be written without halting or disabling peripherals. Writing to CPUDIV allows a new clock setting to be applied simultaneously to all synchronous clocks within the corresponding clock domain.

Figure 11-2. Synchronous Clock Selection and Prescaler