11.4.2 Operation

The GCLK_MAIN clock signal from the GCLK peripheral is the source for the main clock, which is the common root for the synchronous clocks for the CPU, APBx and AHBx peripherals. The GCLK_MAIN can be divided by an 8-bit prescaler. Each of the derived clocks can operate from any divided or undivided main clock, ensuring synchronous clock sources for each clock domain. The CPU clock domain can be changed on the fly to respond to varying application loads. The clocks for each peripheral within a clock domain can be individually masked to reduce power consumption in inactive peripherals. Depending on the sleep mode, some clock domains can be turned off.