11.4.2.4 Clock Ready Flag

There is a slight delay after writing to CPUDIV before the new clock settings become effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) is ‘0’. If the Clock Ready Interrupt Enable bits in the Interrupt Enable Clear and Interrupt Enable Set registers (INTENCLR/SET.CKRDY) are ‘1’, the Clock Ready interrupt will be triggered when the new clock setting is effective. The clock settings must not be rewritten while INTFLAG.CKRDY is ‘0’. The system may become unstable or hang, and a violation is reported to the PAC peripheral.